Barbay Consulting
Single Point Source TM
The New Way of SoC Development
The SPS Tool uses a single point of definition and description of registers written in XML to
be used during the
ASIC/SoC development process and produces multiple output files
which will be used in various ways:

  •  Register Transfer Language (RTL) (Verilog or VHDL).
  •  Embedded firmware for register and bit field definitions in 'C', C++.
  •  HTML documentation with auto-generated links for Register Tables and bit fields.
  •  HTML Chip Memory Map.
  •  HTML Pin I/O Tables using autogenerated  SVG for PIN Pad Graphics.
  • .CSV for legacy.
  •   Validation software:
Read/Write Register testing, Power-On-Reset Register   
Testing written in various language ‘C’,
Vera, System ‘C’, Verilog 'C' and customized       
assembly   language.  

The Single Point Source
XML input file creates an environment where one single input (XML)
defines the registers in a system. SPS uses this XML dialect file to mechinally create
multiple outputs.  This forces a system where outputs dependant on a register change will
be updated and synchronized appropriately.  The outputs created are for a range of
customers within the company and reduces “out-of-synch" errors and miscommunication
across the entire product base of developer's of the ASIC within a company and it's
foundary.  

The SPS approach has SAVED companies MILLIONS of dollars in SoC miscommunication
and silicon turns at the foundary. SPS REDUCES time to market, and REDUCES cost.     
A Leader in SoC Development Tools
Copyright 2008, Lisa K. Barbay