AUDIO Block ADC_SERIAL Module Description

Module Overview: The ADC mdoule is a stereo audio ADC intended for digital audio applications requiring high performance analog-to-digital conversion. It features two 24-bit conversion channels each with programmable gain amplifier (PGA), multibit sigma-delta modulator, and decimation filters. Each channel provides 105 db of dynamic range, making the ADC suitable for applications such as digital audio recorders and mixing consoles. Each of the ADC's input channels (left and right) can be configured as either differential or single-ended (two inputs muxed with internal single-ended-to-differential conversion). The input PGA features a gain range of 0 dB to 12 dB in steps of 3 dB. The Sigma-Delta modulator features a proprietary multibit architecture that realizes optimum performance over an audio bandwidth with standard audio sampling rates of 32 kHz up to 96 kHz. The decimation filter response features very low passband ripple and excellent stop-band attenuation. The ADC's audio data interface supports all common interface formats such as I2S, left-justified, right-justified as well as other modes that allow for convenient connection to general-purpose digital signal processors (DSPs). The ADC also features an SPI compatible serial control port that allows for convenient control of device parameters and functionality such as sample word-width, PGA settings, interface modes, and so on. SPI ADC

ADC_SERIAL Module Register Summary
Register Name	Base Address	POR
ADC_SERIAL_CONTROL_1	0xFFF93000	0x00000000
ADC_SERIAL_CONTROL_2	0xFFF93004	0x00001000
ADC_SERIAL_CONTROL_3	0xFFF93008	0x00002000
ADC_SERIAL_PEAK_RD_1	0xFFF9300C	0x00003580
ADC_SERIAL_PEAK_RD_2	0xFFF93010	0x00004580

ADC_SERIAL Module Registers

ADC_SERIAL_CONTROL_1 Register:	Mode: Normal	Address: 0xFFF93000	POR: 0x00000000
Register Overview: Control Register I contains bit settings for control of analog front end gain, modulator clock selection, power-down control, high-pass filtering, and peak hold.

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Mne
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Mne	ID						PKRD	HIPAF	PWRDN	AMC	ALGN			ARGN

Bit(s)	Mne	Access	Name	Field Description
31:16	RSV	RO	Reserved	Reserved for future use.
15:12	ID	RO	ID	The ID for this register in the ADC_SERIAL Module.
11:10	RSV	RO	Reserved	Reserved for future use.
9	PKRD	R/W	PEAK_RD	Peak Reading Enable bit. Tracks the peak reading on each of the channels (left and right). These 6-bit results are read back via the SPI compatible port in a 16-bit frame similar to that of the control words. 0 = Disabled (Default) 1 = Enabled
8	HIPAF	R/W	HI_PASS_FLTR	High Pass Filter Enable bit. The ADC_SERIAL digital filtering engine allows the insertion of a high-pass filter (HPF) to effectively block dc signals from the output digital waveform. 0 = Disabled (Default) 1 = Enabled High Pass Filter
7	PWRDN	R/W	PWR_DOWN	Power Down Enable bit. In Power-Down Mode, digital activity is suspended and analog sections are powered down, with the exception of the reference. 0 = Normal Operation (Default) 1 = Power Down
6	AMC	R/W	MODULATOR_CLK	Selects the frequency of the modulator clock. The modulator clock can be chosen to be either 128 * f(s)or 64 * f(s). When AMC is set to 0 (default), the modulator clock is 128 * f(s). Otherwise, if set to 1, the modulator clock is 64 * f(s). This bit is normally set depending on whether the desired sampling frequency is 48 kHz or 96 kHz and is also influenced by the selected MCLK frequency. 0 = 128 * f(s) (Default) 1 = 64 * f(s)
5:3	ALGN	R/W	LEFT_GAIN	Optional analog front end with selectable gain. Gain is selected using three control bits for each channel, giving five separate and independent gain settings on each channel. Table for Gains (x represents L or R channel) __________________ AGx2 AGx1 AGx0 Gain (dB) 0 0 0 0 (Default) 0 0 1 3 0 1 0 6 0 1 1 9 1 0 0 12 1 0 1 0 1 1 0 0 1 1 1 0
2:0	ARGN	R/W	RIGHT_GAIN	Optional analog front end with selectable gain. Gain is selected using three control bits for each channel, giving five separate and independent gain settings on each channel. See the Left Gain Table for the settings

ADC_SERIAL_CONTROL_2 Register:	Mode: Normal	Address: 0xFFF93004	POR: 0x00001000
Register Overview: Control Register II contains bit settings for control of left/right channel muting, data sample word width, data interface format, and direct modulator bitstream output.

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Mne
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Mne	ID								MMDE	DTFMT		WRDW		AMC	MUR	MUL

Bit(s)	Mne	Access	Name	Field Description
31:16	RSV	RO	Reserved	Reserved for future use.
15:12	ID	RO	ID	The ID for this register in the ADC_SERIAL Module.
11:8	RSV	RO	Reserved	Reserved for future use.
7	MMDE	R/W	MODULATOR_MODE	Modulator Mode bit. The ADC_SERIAL module defaults to the conversion of the analog audio to linear, PCM-encoded digital outputs. Modulator Mode allows the user to bypass the digital decimation filter section and access the multibit sigma-delta modulator outputs directly. When in this mode, certain pins are redefined and the modulator output (at a nominal rate of 128 * f(s)) is available on the modulator data pins (D[0 : 3]). 0 = Normal Mode (Default) 1 = Modulator enabled. Modulation
6:5	DTFMT	R/W	DATA_FORMAT	The ADC_SERIAL serial data interface can be configured from a choice of popular interface formats, including I2S, left-justified, right-justified, or DSP Modes. Bits DF1-DF0 are programmed to select the interface format (mode). DF0 Interface Mode _____________________________ 0 0 I2S (Default) 0 1 Right-Justified 1 0 DSP 1 1 Left-Justified 0 = Disabled (Default) 1 = Enabled
4:3	WRDW	R/W	WORD_WIDTH	The ADC_SERIAL module allows the output sample word width to be selected from 16, 20, and 24 bits wide. Compact disc (CD) compatibility may require 16 bits, while many modern digital audio formats require 24-bit sample resolution. Bits WW1:WW0 are programmed to select the word width. WW1 WW0 Word Width (No. of Bits) ___________________________________ 0 0 24 (Default) 0 1 20 1 0 16 1 1 Reserved
2	AMC	R/W	MSTR_SLV_CLK	This module can operate as either a slave device or a master device. In Slave Mode, the controller must provide the LRCLK and BCLK to determine the sample rate and serial bit rate. In Master Mode, the ADC_SERIAL module provides the LRCLK and BCLK as outputs that are applied to the controller. This module defaults to Master Mode on reset. 0 = Master Mode(Default) 1 = Slave Mode
1	MUR	R/W	RIGHT_MUTE	The left and right data channels can be muted to digital zero by setting this MUR Bit or the MUL Bit , respectively. If a channel is muted, its output data stream will remain at digital zero, regardless of the amplitude of the input signal. Setting the bit to 1 mutes the channel while setting the bit to 0 restores normal operation. 0 = Right Channel is not muted (Default) 1 = Right Channel is muted.
0:0	MUL	R/W	LEFT_MUTE	See Right Mute Description. 0 = Left Channel is not muted (Default) 1 = Leftt Channel is muted. See RIGHT MUTE description

ADC_SERIAL_CONTROL_3 Register:	Mode: Normal	Address: 0xFFF93008	POR: 0x00002000
Register Overview: Control Register III contains bit settings for configuration of the analog input section (both left and right channels).

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Mne
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Mne	ID								MCD		SEL	SER	MEL	MXL	MER	MXR

Bit(s)	Mne	Access	Name	Field Description
31:16	RSV	RO	Reserved	Reserved for future use.
15:12	ID	RO	ID	The ID for this register in the ADC_SERIAL Module.
11:8	RSV	RO	Reserved	Reserved for future use.
7:6	MCD	R/W	MASTER_CLK_DVD	The master clock divider allows the division of the external MCLK frequency to a more suitable internal master clock frequency (IMCLK). IMCLK must be 256 * f(s); therefore, if the available MCLK is not at 256 * f(s) but is a multiple of this, the MCD allows conversion of MCLK to a suitable IMCLK at 256 * f(s). 7 6 (BITS) MCLK Division 0 0 IMCLK = MCLK (/1) 0 1 IMCLK = MCLK/2 1 0 IMCLK = MCLK/3 1 1 IMCLK = MCLK (/1)
5	SEL	R/W	LSINGLE_END_MODE	The Single-Ended Mode Enable Bits (SEL and SER for left and right channels, respectively), when set to 1, are used to configure single-ended input on VINxP and VINxN (input is selected by state of MXL and MXR). In this mode, single-ended inputs taken from either VINxP or VINxN (selected using the Mux Select Bits MXL and MXR) are internally converted to a differential format to be applied to the modulator section. SEL SER Input Setting 0 X Left Channel Input ->Differential 1 X Left Channel Input ->Single-Ended X 0 Right Channel Input ->Differential X 1 Right Channel Input -> Single-Ended
4	SER	R/W	RSINGLE_END_MODE	See Description of LSINGLE_END_MODE. The SEL bit.
3	MEL	R/W	MUX_LEFT	The Mux Enable Left (MEL) and Mux Enable Right (MER) are used to enable the analog buffers. When these bits are set to 1, the analog input buffers are powered down and input signals must be applied directly to the modulator inputs via the CAPxP and CAPxN pins. When MEL and MER are set to 0 (default condition after reset), the analog input section is enabled. Default is 0 - Left Channel Analog Buffer Enabled. 3 1 (Bit3 = MEL Bit1 = MER)Input Setting 0 X Left Channel Analog Buffer Enabled 1 X Left Channel Analog Buffer Disabled X 0 Right Channel Analog Buffer Enabled X 1 Right Channel Analog Buffer Disabled
2	MXL	R/W	MUX_SELECT_LEFT	The Mux Select Bits (MXL and MXR for left and right channels, respectively) are used to select the input from VINxP or VINxN when the input is configured as single-ended. When MXx is set to 0, the input is taken from VINxP. When MXx is set to 1, the input is taken from VINxN 2 0 (Bits 2[MXL] 0[MXR] Input Setting) 0 X Left Channel Input from VINLP 1 X Left Channel Input from VINLN X 0 Right Channel Input from VINRP X 1 Right Channel Input from VINRN
1	MER	R/W	MUX_RIGHT	Default is 0 - Right Channel Analog Buffer Enabled. The MEL Bit
0	MXR	R/W	MUX_SELECT_RIGHT	Default is 0. The MXL bit.

ADC_SERIAL_PEAK_RD_1 Register:	Mode: Normal	Address: 0xFFF9300C	POR: 0x00003580
Register Overview: The Peak Reading Registers are read-only registers that can be enabled to track-and-hold the peak ADC reading from each channel. The peak reading feature is enabled by setting Bit PRE in Control Register I. The peak reading value is contained in the six LSBs of the 10-bit readback word. The result is binary coded where each LSB is equivalent to -1 dBFS with all zeros corresponding to full scale (0 dBFS) and all ones corresponding to -63 dBFS . When Bit PRE is set, the peak reading per channel is stored in the appropriate peak register. Once the register is read, the register value is set to zero and is updated by subsequent conversions. Control 1 Register

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Mne
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Mne	ID										PKRD1

Bit(s)	Mne	Access	Name	Field Description
31:16	RSV	RO	Reserved	Reserved for future use.
15:12	ID	RO	ID	The ID for this register in the ADC_SERIAL Module.
11:6	RSV	RO	Reserved	Reserved for future use.
5:0	PKRD1	RO	PEAK_RD_FMT	Left Channel Peak Reading (Valid when PRE == 1). Bits 5-0 AxP (x =Left or Right) 5 4 3 2 1 0 0 0 0 0 0 0 = 0dBFS Level 0 0 0 0 0 1 = -1 dBFS Level 0 0 0 0 1 0 = -2 dBFS Level .... (-3 to -61 dBFS Level 1 1 1 1 1 0 = -62 dBFS Level 1 1 1 1 1 1 = -64 dBFS Level See PRE bit

ADC_SERIAL_PEAK_RD_2 Register:	Mode: Normal	Address: 0xFFF93010	POR: 0x00004580
Register Overview: Peak Read 2 Register for the Right Channel. Peak Read 1 Register

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Mne
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Mne	ID										PKRD2

Bit(s)	Mne	Access	Name	Field Description
31:16	RSV	RO	Reserved	Reserved for future use.
15:12	ID	RO	ID	The ID for this register in the ADC_SERIAL Module.
11:6	RSV	RO	Reserved	Reserved for future use.
5:0	PKRD2	RO	PEAK_RD_FMT	Right Channel Peak Reading (Valid when PRE == 1). See Peak Read 1 Reg