AUDIO Block DAC Module Description
Module Overview: The DAC module is a circuit which includes stereo digital-to-analog conversion. The data converters use enhanced multilevel delta-sigma that employes fourth order noise shaping and 8 level amptitude quantization to achieve excellent dynamic performance and improved tolerance to clock jitter. This module uses industry audio data formats for 16-bit to 24-bit data, providing an easy interface with the audio dsp. Sampling rates up to 100 kHz are supported by programmable registers. This module uses a 3 pin serial interface.
DAC


DAC Module Register Summary
Register Name Base Address POR
DAC_DIGITAL_LEVEL_LEFT 0xFFF93400 0x00FF
DAC_DIGITAL_LEVEL_RIGHT 0xFFF93402 0x00FF
DAC_MUTE_CTRL 0xFFF93404 0x00000000
DAC_DAC_CTRL 0xFFF93408 0x00000000
DAC_INTERFACE_FMT 0xFFF9340C 0x00000000
DAC_CONFIG 0xFFF93410 0x00000000

DAC Module Registers
DAC_DIGITAL_LEVEL_LEFT Register: Mode: Normal Address: 0xFFF93400 POR: 0x00FF
Register Overview: ATx[7:0] Digital Attenuation Level Setting for the Left Channel. Each DAC channel (VOUTL and VOUTR) includes a digital attenuator function. The attenuation level can be set from 0 dB to -63 dB in 0.5-dB steps. Changes in attenuation levels are made by incrementing or decrementing, by one step (0.5 dB), for every 8/fS time interval until the programmed attenuator setting is reached. Alternatively, the attenuation level can be set to infinite attenuation, or mute. The attenuation data for each channel can be set individually.
About attenuation
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne ALLFT
Bit(s) Mne Access Name Field Description
15:8 RSV RO Reserved Reserved for future use.
7:0 ALLFT R/W ATLVL_LEFT The attenuation level is calculated using the following formula: Attenuation level (dB) = 0.5 (ATx[7:0](DECIMAL) -255) where ATx[7:0]DEC = 0 through 255 and x represent Left or Right Channel. For ATx[7:0]DEC = 0 through 128, the attenuator is set to infinite attenuation. The following table shows attenuator levels for various settings.
ATx[7:0] DECIMAL VALUE ATTENUATOR LEVEL SETTING
1111 1111b 255 0 dB, no attenuation (default)
1111 1110b 254 -0.5 dB
1111 1101b 253 -1 dB
...
1000 0011b 131 -62 dB
1000 0010b 130 -62.5 dB
1000 0001b 129 -63 dB
1000 0000b 128 Mute
....
0000 0000b 0 Mute


DAC_DIGITAL_LEVEL_RIGHT Register: Mode: Normal Address: 0xFFF93402 POR: 0x00FF
Register Overview: ATx[7:0] Digital Attenuation Level Setting for the Right Channel.
See the Digital Level Left
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne ALRGT
Bit(s) Mne Access Name Field Description
15:8 RSV RO Reserved Reserved for future use.
7:0 ALRGT R/W ATLVL_RIGHT The attenuation level is calculated using the following formula: Attenuation level (dB) = 0.5 (ATx[7:0](DECIMAL) -255) where ATx[7:0]DEC = 0 through 255 and x represent Left or Right
See ATLVL_LEFT for Table


DAC_MUTE_CTRL Register: Mode: Normal Address: 0xFFF93404 POR: 0x00000000
Register Overview: Soft Mute Control for Left and Right Channels.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne OVER MUT2 MUT1
Bit(s) Mne Access Name Field Description
31:7 RSV RO Reserved Reserved for future use.
6 OVER R/W OVER
OVER = 0 64x oversampling (default)
OVER = 1 128x oversampling
The OVER bit is used to control the oversampling rate of the delta-sigma DACs.
5:2 RSV RO Reserved Reserved for future use.
1 MUT2 R/W RIGHT_EN
MUT2 = 0, Mute disabled for Right Channel
MUT2 = 1, Mute enabled for Right Channel

Mute Control for Left Channel
0 MUT1 R/W LEFT_EN The mute bits, MUT1 and MUT2, are used to enable or disable the soft mute function for the corresponding DAC outputs, VOUTL and VOUTR. The soft mute function is incorporated into the digital attenuators. When mute is disabled (MUTx = 0), the attenuator and DAC operate normally. When mute is enabled by setting MUTx = 1, the digital attenuator for the corresponding output is decreased from the current setting to the infinite attenuation setting by one attenuator step (0.5 dB) at a time for every 8/fS period. This provides a quiet, pop-free muting of the DAC output. By setting MUTx = 0, the attenuator is increased by one step for every 8/fS period to the previously programmed attenuation
MUT1 = 0, Mute disabled for Left Channel
MUT1 = 1, Mute enabled for Left Channel


DAC_DAC_CTRL Register: Mode: Normal Address: 0xFFF93408 POR: 0x00000000
Register Overview: DAC Control for Left and Right Channels.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne DFRGT DFLFT DM12 DAC2 DAC1
Bit(s) Mne Access Name Field Description
31:7 RSV RO Reserved Reserved for future use.
6:5 DFRGT R/W DF_RIGHT Sample Rate select for the de-emphasis function for the Right channel
DMF[1:0] De-Emphasis Sample Rate Selection
00 44.1 kHz (default)
01 48 kHz
10 32 kHz
11 Reserved
4:3 DFLFT R/W DF_LEFT Sample Rate select for the de-emphasis function for the Left channel
DMF[1:0] De-Emphasis Sample Rate Selection
00 44.1 kHz (default)
01 48 kHz
10 32 kHz
11 Reserved
2 DM12 R/W DIGITAL_DEMPHASIS Turn on the digital de-emphasis function for both the left and the right channels.
1 DAC2 R/W DISABLE2
DAC2 = 0, DAC enabled for Right Channel
DAC2 = 1, DAC disabled for Right Channel

DAC Control for Left Channel
0 DAC1 R/W DISABLE1 The DAC operation controls are used to enable and disable the DAC outputs, VOUTL and VOUTR. When DACx = 0, the corresponding output generates the audio waveform dictated by the data present on the DATA pin. When DACx = 1, the corresponding output is set to the bipolar zero level, or VCC.
DAC1 = 0, DAC Enabled for Left Channel
DAC1 = 1, DAC Disabled for Left Channel


DAC_INTERFACE_FMT Register: Mode: Normal Address: 0xFFF9340C POR: 0x00000000
Register Overview: Audio Interface format for Left and Right Channels.,
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne FLT DTFMT
Bit(s) Mne Access Name Field Description
31:6 RSV RO Reserved Reserved for future use.
5 FLT R/W FILTER_CTRL Digital Filter Rolloff Control.
FLT = 0 Sharp Rolloff (default).
FLT = 1 Slow Rolloff.
4:3 RSV RO Reserved Reserved for future use.
2:0 DTFMT R/W DATA_FMT Serial Audio Data Format Selection for both channels.

FMT[2:0] Audio Data Format Selection
000 24-bit standard format, right-justified data
001 20-bit standard format, right-justified data
010 18-bit standard format, right-justified data
011 16-bit standard format, right-justified data
100 I2S format, 16- to 24-bit
101 Left-justified format, 16- to 24-bit (default)
110 Reserved
111 Reserved


DAC_CONFIG Register: Mode: Normal Address: 0xFFF93410 POR: 0x00000000
Register Overview: General Configuration for the DAC.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne AZRO ZREV DREV
Bit(s) Mne Access Name Field Description
31:3 RSV RO Reserved Reserved for future use.
2 AZRO R/W ZERO_FLG_FXN
AZRO = 0 L-/R-channel independent zero flags (default)
Pin 11: ZEROR = zero-flag output for R-channel
Pin 12: ZEROL = zero flag output for L-channel

AZRO = 1 L-/R-channel common zero flag
Pin 11: ZEROA = zero flag output for L-/R-channel
Pin 12: NA, not assigned
1 ZREV R/W ZERO_FLG_POLARITU The ZREV bit allows the user to select the active polarity of zero-flag pins.
ZREV = 0 Zero-flag pins HIGH at a zero detect (default)
ZREV = 1 Zero-flag pins LOW at a zero detect
0 DREV R/W OUT_PHASE The DREV bit is used to set the output phase of VOUTL and VOUTR.

DREV = 0 Normal output (default)
DREV = 1 Inverted output