AUDIO Block I2S Module Description
Module Overview: The I2S module provides an interface between the chip it resides in and the outside DACs or other interfaces using the I2S (Inter Connect sound) protocol to transfer audio data. Some typical external input sources are A/D converters, or high performance audio processors. It is currently implemented with 6 receive ports and 6 transmit ports. All ports work as the master of the protocol, i.e. clocks are generated from the I2S module. Slave mode is not supported in the current design.

The current I2S audio interface supports the following features:

o Always a bus master, responsible for bit clock and Left/Right clock generation.
o Master clock to left/right clock ratios: 64, 128, 256
o Supports programmable sample rates of: 32 KHz, 44.1KHz, 48KHz, 96KHz, and 192KHz
o Receiver data width: up to 24 bits; Transmitter data width: always 24 bits.
o 6 receive ports, 6 transmit ports
o For transmit, all TX ports operate off the same transmit clock, while for receive,
all RX ports operate off the same receive clock. The transmit clock and
receive clock can be programmed to run in different sampling rates.
o Mute control on transmit ports.
o 16 FIFO levels for TX data buffering.
o 2 modes of transferring data into FIFO: DMA mode and direct access mode.
o Supports loopback mode for testing.

For transmit, I2S always outputs audio data in word lengthof 24 bits. And the MSB is always sent first. For receive,it supports any length up to 24 bits. If the received word length is less than that, zero padding is applied to the LS bits. If the received word length is more than that, the I2S receiver will only keep the MS 24 bits dropping the remaining lower order bits.
Phillip's I2s Specification


I2S Module Register Summary
Register Name Base Address POR
I2S_STATUS 0xFFF90000 0x00000000
I2S_FIFO_STATUS 0xFFF90004 0x00000000
I2S_CONFIG 0xFFF90008 0x00000000
I2S_RX_DATA0 - I2S_RX_DATA5 0xFFF9000C, 0xFFF90014, 0xFFF9001C, 0xFFF90024
0xFFF9002C, 0xFFF90034
0x00000000
I2S_TX_DATA0 - I2S_TX_DATA5 0xFFF90010, 0xFFF90018, 0xFFF90020, 0xFFF90028
0xFFF90030, 0xFFF90038
0x00000000
I2S_CLOCK 0xFFF90050 0x00000000
I2S_FIFO0 - I2S_FIFO5 0xFFF90100, 0xFFF90104, 0xFFF90108, 0xFFF90110
0xFFF90114, 0xFFF90118
0x00000000

I2S Module Registers
I2S_STATUS Register: Mode: Normal Address: 0xFFF90000 POR: 0x00000000
Register Overview: This register contains the status of the I2S module. It has status bits for DMA for each of the I2S ports and information about the I2S fifo.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne RXOVF
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne RDR TDR
Bit(s) Mne Access Name Field Description
31:22 RSV RO Reserved Reserved for future use.
21:17 RXOVF RO RX_OVRFLOW The I2S_RX(n)_DATA has not been read by DMA in the required time, and will be overwritten by new incoming data. To clear it, read the I2S_RX(n)_DATA register or disable the port.
See RX_DATA register details.
16:12 RSV RO Reserved Reserved for future use.
11:6 RDR RO RX_DMA_READY RX Port N has just received an audio word and requests a new DMA transfer. The bit (n) is cleared after a read on the I2S_RX(n)_DATA register either by the DMA or by the processor.
5:0 TDR RO TX_DMA_READY TX Port N has just transmitted an audio word and requests a new DMA transfer. The bit (n) is cleared after a write to the FIFO. The field is valid only in DMA_mode.


I2S_FIFO_STATUS Register: Mode: Normal Address: 0xFFF90004 POR: 0x00000000
Register Overview: This register contains information about the fifo status.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne FFUL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne FFEMP
Bit(s) Mne Access Name Field Description
31:22 RSV RO Reserved Reserved for future use.
21:16 FFUL RO FIFO_FULL
1 = The FIFO of the corresponding TX Port N is full.
0 = The FIFO of the corresponding TX Port N empty.
15:6 RSV RO Reserved Reserved for future use.
5:0 FFEMP RO FIFO_EMPTY
1 = The FIFO of the corresponding TX Port N is empty.
In normal operation, it is not expected to be set.
0 = The FIFO of the corresponding TX Port N contains
valid data and is not empty.


I2S_CONFIG Register: Mode: Normal Address: 0xFFF90008 POR: 0x00000000
Register Overview: This register contains all the configuration bits and control bits for the I2S module.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne LPBK AMOD CLRFF
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne TMU TXEN RXEN
Bit(s) Mne Access Name Field Description
31:28 RSV RO Reserved Reserved for future use.
27 LPBK R/W LOOPBACK Loops the TX(N) to RX(N) for testing transmit and receive.

Internal:
This is for testing purposes only
26:23 AMOD R/W ACCESS_MODE
1 = Direct_access mode that uses the fifo .
0 = DMA mode or processor access. Fifo is not used.
22:22 CLRFF R/W CLEAR_FIFO Clears fifo_full/empty flags, resets write/read pointers to zeros.
21:17 RSV RO Reserved Reserved for future use.
16:12 TMU R/W TX_MUTE When the transmit port is enabled and this bit is set, the transmit port outputs zeros, thus muting the transmit.
11:6 TXEN R/W TX_ENABLE
1 = Transmit Port N is enabled.
0 = Transmit Port N is disabled.
If none of the transmit ports are enabled, then I2s clock generation is stopped.
See TX DATA register.
5:0 RXEN R/W RX_ENABLE
1 = Receive Port N is enabled.
0 = Receive Port N is disabled.
If none of the receive ports are enabled, then I2s clock generation is stopped.
See RX DATA register.


I2S_RX_DATA0 - I2S_RX_DATA5 Registers: Mode: Normal Addresses:
0xFFF9000C, 0xFFF90014,
0xFFF9001C, 0xFFF90024,
0xFFF9002C, 0xFFF90034
POR: 0x00000000
Register Overview: If the RX Port N is enabled, the RX Data Port N contains the received data.
RX Enable bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne AWORD
Bit(s) Mne Access Name Field Description
31:24 RSV RO Reserved Reserved for future use.
23:0 AWORD RO AUDIO_WORD Up to 24-bit audio word received by the I2S module.


I2S_TX_DATA0 - I2S_TX_DATA5 Registers: Mode: Normal Addresses:
0xFFF90010, 0xFFF90018,
0xFFF90020, 0xFFF90028,
0xFFF90030, 0xFFF90038
POR: 0x00000000
Register Overview: For each of the enabled TX Port N, a valid audio word is ready to be transmitted.
TX Enable bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne AWORD
Bit(s) Mne Access Name Field Description
31:24 RSV RO Reserved Reserved for future use.
23:0 AWORD RO AUDIO_WORD A 24-bit audio word to be transmitted by the I2S module.


I2S_CLOCK Register: Mode: Normal Address: 0xFFF90050 POR: 0x00000000
Register Overview: Controls for I2S Master clock generation, Left/Right controls, and sample rate for the transmit clock
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne TXSRT MCLK LRCLK
Bit(s) Mne Access Name Field Description
31:6 RSV RO Reserved Reserved for future use.
5:3 TXSRT R/W TX_SAMPLE_RATE Select the Transmit clock sample rate. Values 5-7 are reserved.

Enumerations for eI2sTxSampleRate:
eI2sTxRate32 = 0 ; I2s TX sampling rate is set to 32Khz.
eI2sTxRate44_1 = 1 ; I2s TX sampling rate is set 44.1 Khz.
eI2sTx48 = 2 ; I2s TX sampling rate is set to 48 Khz.
eI2sTx96 = 3 ; I2s TX sampling rate is set to 96 Khz.
eI2sTX192 = 4 ; I2s TX sampling rate is set to 192 Khz.
2:1 MCLK R/W MASTER Select the master clock ratio. A value of 3 is reserved.

Enumerations for eI2sMasterClkRatio:
eI2sMClk64 = 0 ; Master Clock Ratio is set to 64
eI2sMClk128 = 1 ; Master Clock Ratio is set to 128
eI2sMClk256 = 2 ; Master Clock Ratio is set to 256
0 LRCLK R/W LR_CLK Select which clock to send out first Left or Right on Transmit


I2S_FIFO0 - I2S_FIFO5 Registers: Mode: Normal Addresses:
0xFFF90100, 0xFFF90104,
0xFFF90108, 0xFFF90110,
0xFFF90114, 0xFFF90118
POR: 0x00000000
Register Overview: 16 Buffered audio words for each the N Ports.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne FFWRD
Bit(s) Mne Access Name Field Description
31:24 RSV RO Reserved Reserved for future use.
23:0 FFWRD R/W AUDIO_WORD This field contains the audio fifo data. Each entry in the corresponding N fifo is is a 24 bit audio word.