DRAM Block EMIF Module Description

Module Overview: This describes all the registers in the External Memory Interface (EMIF) Module. The Memory Controller is a BVCI peripheral. It contains the SRAM controller and SDRAM controller. Only one of the two controller can be active at the same time, because they are sharing address and data pins on the bulldog chip.

EMIF Module Register Summary
Register Name	Base Address	POR
EMIF_MEM_CTRL_ID	0xFFFA0000	0x0000FB06
EMIF_RD_CFG_CS0 - EMIF_RD_CFG_CS3	0xFFFA0020, 0xFFFA0024, 0xFFFA0028, 0xFFFA002C	0x00000000
EMIF_WR_CFG_CS0 - EMIF_WR_CFG_CS3	0xFFFA0040, 0xFFFA0044, 0xFFFA0048, 0xFFFA004C	0x00000000
EMIF_SELECT_CS0 - EMIF_SELECT_CS3	0xFFFA0060, 0xFFFA0064, 0xFFFA0068, 0xFFFA006C	0x00000000
EMIF_INT_ROM_DISABLE	0xFFFA6040	0x00000000
EMIF_SDRAM_CONFIG	0xFFFA6044	0x02F00038
EMIF_SDRAM_MODE	0xFFFA6048	0x00000031

EMIF Module Registers

EMIF_MEM_CTRL_ID Register:	Mode: Normal	Address: 0xFFFA0000	POR: 0x0000FB06
Register Overview: The Identification register (ID) provides a simple way to determine if the memory controller is provided in the ARC sub-system. The ID register identifies the ARC memory controller and its revision.

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Mne									AREV
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Mne			ANID								AID

Bit(s)	Mne	Access	Name	Field Description
31:24	RSV	RO	Reserved	These bits are reserved and should be set to zero.
23:16	AREV	RO	Revision	The revision number of the ARC memory controller.
15:14	RSV	RO	Reserved	These bits are reserved, they must be tied to 1.
13:8	ANID	RO	NEGATE_ID	1's complement of the ID field.
7:6	RSV	RO	RSV	Constantly tied to 0.
5:0	AID	RO	CONFIG_ID	Configuration number. This number is set to 0x06 and indicates that the peripheral is the memory controller.

EMIF_RD_CFG_CS0 - EMIF_RD_CFG_CS3 Registers:	Mode: Normal	Addresses: 0xFFFA0020, 0xFFFA0024, 0xFFFA0028, 0xFFFA002C	POR: 0x00000000
Register Overview: There are 4 instances of this Read Configuration CSx. Each read configuration register configures the number of clock cycles for each phase of the external memory read for each of the memory device which are tied to Chip Select 0-3.

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Mne				ARSTP								ARACS
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Mne				ARHT								ARIT

Bit(s)	Mne	Access	Name	Field Description
31:29	RSV	R/W	Reserved	Reserved, always write this field to a zero.
28:24	ARSTP	R/W	Rsetup_Time	Number of clocks in the setup stage for read.
23:21	RSV	R/W	Reserved	Reserved, always write this field to a zero.
20:16	ARACS	R/W	Raccess_Time	Number of clocks in the access stage for read.
15:13	RSV	R/W	Reserved	Reserved, always write this field to a zero.
12:8	ARHT	R/W	Rhold_Time	Number of clocks in the hold stage for read.
7:5	RSV	R/W	Reserved	Reserved always write this field to a zero.
4:0	ARIT	R/W	Ridle_Time	Number of clocks in the Hi-Z stage (between back-t-back read).

EMIF_WR_CFG_CS0 - EMIF_WR_CFG_CS3 Registers:	Mode: Normal	Addresses: 0xFFFA0040, 0xFFFA0044, 0xFFFA0048, 0xFFFA004C	POR: 0x00000000
Register Overview: There are 4 instances of this Write Configuration CSx. Each write configuration register configures the number of clock cycles for each phase of the external memory read for each of the memory device which are tied to Chip Select 0-3.

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Mne				AWSTP								AWACS
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Mne				AWHT								ARIT

Bit(s)	Mne	Access	Name	Field Description
31:29	RSV	R/W	Reserved	This is reserved, and must be written to zero.
28:24	AWSTP	R/W	Wsetup_Time	Number of clocks in the setup stage for write.
23:21	RSV	R/W	Reserved	This is reserved, and must be written to zero.
20:16	AWACS	R/W	Waccess_Time	Number of clocks in the access stage for write.
15:13	RSV	R/W	Reserved	This is reserved, and must be written to zero.
12:8	AWHT	R/W	Whold_Time	Number of clocks in the hold stage for write.
7:5	RSV	R/W	Reserved	This is reserved, and must be written to zero.
4:0	ARIT	R/W	Widle_Time	Number of clocks in the Hi-Z stage (between back-t-back write).

EMIF_SELECT_CS0 - EMIF_SELECT_CS3 Registers:	Mode: Normal	Addresses: 0xFFFA0060, 0xFFFA0064, 0xFFFA0068, 0xFFFA006C	POR: 0x00000000
Register Overview: This register defines the decoding range and the interface width of each of the asynchronous memory components connected to CS[0:3] lines.

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Mne	AMASK
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Mne	ALOC															ADW

Bit(s)	Mne	Access	Name	Field Description
31:24	AMASK	R/W	Addr_Mask	This field represents the top 8 bits of the total available address space for the memory controller. If MASK is set to '0' (and by implication LOCATE (Lo_Cs field) is set to '0'), the whole address range is available for the Bulldog chip.
23:16	RSV	R/W	Reserved	This field is reserved for future use.
15:8	ALOC	R/W	Lo_Cs	Location of the chip select. The LOCATE (Lo_Cs) field represents the top 8 bits of the total available address space for the memory controller. Note: any bits that are '0' in the MASK field MUST be '0' in this field.
7:1	RSV	R/W	Reserved	This field is reserved for future use.
0	ADW	R/W	Data_Width	1 bit field that describes the width of data bus. Enumerations for teSelectCsDataWidth:

EMIF_INT_ROM_DISABLE Register:	Mode: Normal	Address: 0xFFFA6040	POR: 0x00000000
Register Overview: This register disables the internal ROM access, if the internal ROM was selected at bootup. If the internal ROM was not selected, this register has no effect

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Mne
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Mne																IRDIS

Bit(s)	Mne	Access	Name	Field Description
31:1	RSV	RO	Reserved	Reserved, always zero
0	IRDIS	R/W	Int_ROM_disable	Write '1' to disable the internal bootstrap ROM

EMIF_SDRAM_CONFIG Register:	Mode: Normal	Address: 0xFFFA6044	POR: 0x02F00038
Register Overview: This register defines the characteristics of the SDRAM interface

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Mne	IDONE				RFCNT
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Mne								SRFSH	PWDN	TRCD	DB16	QBANK	RWDTH		CWDTH

Bit(s)	Mne	Access	Name	Field Description
31:31	IDONE	RO	Init_done	This field will return '1' when the initialization sequence of the SDRAM interface is completed. The host firmware should not start any access to the SDRAM chip until this bit is set
30:28	RSV	RO	Reserved	This field is reserved for future use.
27:16	RFCNT	R/W	refresh_count	This field defines the number of clock cycles between two consecutive refreshes on the SDRAM interface. This value must be smaller than or equal to the required maximum value required by the SDRAM device
15:9	RSV	RO	Reserved	This field is reserved for future use.
8	SRFSH	R/W	self_refresh	Writing '1' will turn on self-refresh for the SDRAM. The host firmware can turn off the SDRAM clock afterwards
7	PWDN	R/W	power_down	Writing '1' will turn on self-refresh for the SDRAM. CKE pin will go low and the host firmware can turn off the SDRAM clock afterwards. To exit self-refresh mode, write '0' to this bit.
6	TRCD	R/W	Trcd	Writing '1' will add 1 more clock cycle between RAS and CAS cycles on the SDRAM command interface
5	DB16	R/W	Data_bus_width	Writing '1' in this bit will force the SDRAM controller to read/write data over the pins D[15:0]. This bit must be properly configured to match with the system board configuration
4	QBANK	R/W	Quad_bank	Writing '1' in this field indicates the SDRAM being used has 4 banks
3:2	RWDTH	R/W	Row_width	Defines the number of bits for the row address of the SDRAM. This field must be properly programmed to match with the actual arrangement of the SDRAM device used in the system. 00:11 bits for the row address 01: 12 bits for the row address 10: 13 bits for the row address 11: illegal setting Enumerations for teSdramRowWidth:
1:0	CWDTH	R/W	Column_width	Combining with the value of RWIDTH, this field defines the width of the column address under different row-address width. This field must be properly programmed to match with the actual arrangement of the SDRAM device used in the system. if RWIDTH=00 00: 8 bits for the column address 01: 9 bits for the column address 10: 10 bits for the column address 11: illegal if RWIDTH=01 00: 8 bits for the column address 01: 9 bits for the column address 10: 10 bits for the column address 11: 11 bits for the column address if RWIDTH=10 00: 9 bits for the column address 01: 10 bits for the column address 10: 11 bits for the column address 11: 12 bits for the column address

EMIF_SDRAM_MODE Register:	Mode: Normal	Address: 0xFFFA6048	POR: 0x00000031
Register Overview: This register defines the characteristics of the SDRAM chip behavior. More information can be found in the data sheet of any SDR (Single data rate) SDRAM devices

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Mne
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Mne							WBM	OPMDE		CASLT			BT	BL

Bit(s)	Mne	Access	Name	Field Description
31:10	RSV	RO	Reserved	This field is always zero
9	WBM	R/W	Write_burst_mode	Defines the characteristic when writing to the SDRAM (Burst mode or single location), Enumerations for teWrBurstMode:
8:7	OPMDE	R/W	Operating_mode	Only write "00" to this mode for standard operation. All other settings are reserved
6:4	CASLT	R/W	CAS_Latency	Defines the number of clocks after the issue of CAS that the read data is available at the DQ pin of the SDRAM device. Only "010" and "011" are supported. Writing othe values to this field will give unpredictable results.
3	BT	R/W	Burst_type	Defines the burst type when accessing the SDRAM device. Only the sequential type is supported
2:0	BL	R/W	Burst_length	Defines the number of SDRAM locations to be accessed when a column address is issued. This value should be tightly coupled with the external data bus width of the SDRAM being used. If DB16=0, set BL to "000" for burst length of 1. If DB16=1, set BL="001" for burst length of 2. Other settings are not supported by the SDRAM controller and will create unpredictable results.