SOC Block ARC_TIMERs 0-1 Module Description
Module Overview: Timer Module for ARC5 Described in Ancillary Ref Document. These timers use the auxillary mode for accessing them. Their optional ADDR_MODE should be set to AUX.


ARC_TIMER Module Register Summary
Register Name Base Address POR
ARC_TIMER0_COUNT - ARC_TIMER1_COUNT 0xFFFC1000, 0xFFFC1100
0x00000000
ARC_TIMER0_CONTROL - ARC_TIMER1_CONTROL 0xFFFC1000, 0xFFFC1100
0x00000000
ARC_TIMER0_LIMIT - ARC_TIMER1_LIMIT 0xFFFC1008, 0xFFFC1108
0x00000000

ARC_TIMER Module Registers
ARC_TIMER0_COUNT - ARC_TIMER1_COUNT Registers: Mode: AUX Addresses:
0xFFFC1000, 0xFFFC1100
POR: 0x00000000
Register Overview: The Timer count value is a read/write register. Writing to this register sets the initial count value for the timer. Subsequently, the register can be read to reflect the timer N (0 or 1) count progress.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne TCNT
Bit(s) Mne Access Name Field Description
31:0 TCNT R/W VALUE See register Description.
TIMER_COUNT Register


ARC_TIMER0_CONTROL - ARC_TIMER1_CONTROL Registers: Mode: AUX Addresses:
0xFFFC1000, 0xFFFC1100
POR: 0x00000000
Register Overview: Control Bits for the timers
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne TIE TNHE TWDE
Bit(s) Mne Access Name Field Description
31:3 RSV RO Reserved Reserved.
2 TIE R/W Interrupt_Enable If set, enables the generation of an interrupt after the timer has reached its limit condition. If not set, no interrupt is generated.
1 TNHE R/W Not_Halted_Mode If set, cause the timer to count only when the processor is not halted. When not set, every clock is counted even when the processor is halted.
0:0 TWDE R/W Watchdog_Mode If set enables the generation of a system reset signal after the timer has reached its limit condition. If this bit is not set then no watchdog reset will be generated. Note that the reset signal is activated two cycles after the limit condition has been reached.


ARC_TIMER0_LIMIT - ARC_TIMER1_LIMIT Registers: Mode: AUX Addresses:
0xFFFC1008, 0xFFFC1108
POR: 0x00000000
Register Overview: Contains the Limit Value for which an interrupt will be generated, if the timer interrupt bit is enabled in TIMER_CONTROL Register.
TIMER_CONTROL Register
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne TLV
Bit(s) Mne Access Name Field Description
31:0 TLV R/W VALUE The Timer Limit value is a read/write register. The programmer should write the limit value into this register. The limit value is the value after which an interrupt is to be generated.
Timer Int Enable bit