SOC Block ARC_UARTs 0-1 Module Description
Module Overview: This describes all the registers in the ARC VUART Module. This describes all the registers in the ARC VUART Module. The transmit logic waits for the ARCtangent-A5 processor to load a byte into the TX_HOLD register. This byte is transferred into the TX_SHIFT register and the TX_BIT_CTR begins running and the start bit is output on TX_DATA. Once all 10 bits (start, 8 data, stop bits) have been shifted, the next byte is immediately loaded into the TX_SHIFT register if another byte is available in the TX_HOLD register. register. If TXENB=1 then when TXEMPTY=1 the interrupt line is active. TXEMPTY is cleared by writing to the DataTX register. The receive logic is more complex than transmit as it must synchonize to the incoming data stream. RX_DATA is first synchronized twice to eliminate metastability problems. Then the RX_BIT_CTR begins running and the current "phase" of the 4X clock is sampled. This allows sampling of each bit at the 1/2 to 3/4 point in the bit. Once all 10 bits have been shifted in, the start and stop bits are checked and the framing error is activated if they are not correct. The data is transferred into the RX _FIFO register and another byte can be received while the ARCtangent-A5 is reading the RX_FIFO register. If RXENB=1 then when a character is received and placed in the FIFO, RXEMPTY goes to zero and an interrupt is generated. RXOFLO and RXFRAM also set the interrupt line active. RXEMPTY is automatically set/cleared by RxFifo logic. RXEMPTY is set to 1 anytime the RxFIFO is empty. RXEMPTY is cleared when a chracter is received and loaded into the FIFO. Reading the RxDATA register sets RXEMPTY high again once all characters have been read out of the FIFO. RXOFLO and RXFRAM are set by hardware but must be written with zero by software to clear the bit. The VUART has a receive FIFO with a depth of 4.

ARC_UART Module Register Summary
Register Name	Base Address	POR
ARC_UART0_ID0 - ARC_UART1_ID0	0xFFFB0000, 0xFFFB1000	0x00000001
ARC_UART0_ID1 - ARC_UART1_ID1	0xFFFB0004, 0xFFFB1004	0x0000003E
ARC_UART0_ID2 - ARC_UART1_ID2	0xFFFB0008, 0xFFFB1008	0x00000000
ARC_UART0_ID3 - ARC_UART1_ID3	0xFFFB000C, 0xFFFB100C	0x00000000
ARC_UART0_DATA - ARC_UART1_DATA	0xFFFB0010, 0xFFFB1010	0x00000000
ARC_UART0_STATUS - ARC_UART1_STATUS	0xFFFB0014, 0xFFFB1014	0x00000000
ARC_UART0_BAUD_LO - ARC_UART1_BAUD_LO	0xFFFB0018, 0xFFFB1018	0x00000000
ARC_UART0_BAUD_HI - ARC_UART1_BAUD_HI	0xFFFB001C, 0xFFFB101C	0x00000000

ARC_UART Module Registers

ARC_UART0_ID0 - ARC_UART1_ID0 Registers:	Mode: Normal	Addresses: 0xFFFB0000, 0xFFFB1000	POR: 0x00000001
Register Overview: The register contains the Configuration number .

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Mne
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Mne											CFG

Bit(s)	Mne	Access	Name	Field Description
31:6	RSV	RO	Reserved	Reserved for future use.
5:0	CFG	RO	Config	This number is set to 0x01 and indicates that the peripheral is the UART.

ARC_UART0_ID1 - ARC_UART1_ID1 Registers:	Mode: Normal	Addresses: 0xFFFB0004, 0xFFFB1004	POR: 0x0000003E
Register Overview: This register contains the Not ID Configuration number.

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Mne
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Mne											NCFG

Bit(s)	Mne	Access	Name	Field Description
31:6	RSV	RO	Reserved	Reserved for future use.
5:0	NCFG	RO	NID	Ones complement of the ID0 field.

ARC_UART0_ID2 - ARC_UART1_ID2 Registers:	Mode: Normal	Addresses: 0xFFFB0008, 0xFFFB1008	POR: 0x00000000
Register Overview: This register contains the revision number of the UART.

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Mne
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Mne									NREV

Bit(s)	Mne	Access	Name	Field Description
31:8	RSV	RO	Reserved	Reserved for future use.
7:0	NREV	RO	Revision	Current UART revision.

ARC_UART0_ID3 - ARC_UART1_ID3 Registers:	Mode: Normal	Addresses: 0xFFFB000C, 0xFFFB100C	POR: 0x00000000
Register Overview: Reserved for future use.

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Mne
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Mne

Bit(s)	Mne	Access	Name	Field Description
31:0	RSV	RO	Reserved	Reserved for future use.

ARC_UART0_DATA - ARC_UART1_DATA Registers:	Mode: Normal	Addresses: 0xFFFB0010, 0xFFFB1010	POR: 0x00000000
Register Overview: Data Transmitting register or Data Receive register.

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Mne
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Mne									UTXRX

Bit(s)	Mne	Access	Name	Field Description
31:8	RSV	RO	Reserved	Reserved for future use.
7:0	UTXRX	RO	tx_rx	TX_DATA = Byte data transmitted by the UART when transmitting. (R/W) RX_DATA = Byte received by UART when receiving.

ARC_UART0_STATUS - ARC_UART1_STATUS Registers:	Mode: Normal	Addresses: 0xFFFB0014, 0xFFFB1014	POR: 0x00000000
Register Overview: Status of the UART state machine.

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Mne
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Mne									UTXE	UTXB	URXE	URXF1	URXF	URXB	URXO	URXM

Bit(s)	Mne	Access	Name	Field Description
31:8	RSV	RO	Reserved	Reserved for future use.
7	UTXE	RO	tx_empty	TX holding register empty. (read only) Equals 1 if DataTX is empty and can be written to. Equals 0 if DataTx is full and the user should not write data.
6	UTXB	R/W	tx_enb	TX Interrupt Enable. If 1 then TXEMPTY=1 will interrupt. If 0 the interrupt will not propogate to the ARC's interrupt controller. The status will still be set if the the transmitting buffer is empty.
5	URXE	RO	rx_empty	RxFIFO Empty. (read only) Equals 1 if RxFIFO is empty. Automatically cleared when data is read from Rx Data register.
4	URXF1	RO	rx_full1	RxFIFO Full minus 1. Equals 1 if Rx FIFO is full minus 1.
3	URXF	RO	rx_full	RxFIFO Full minus 1. Equals 1 if Rx FIFO is full.
2	URXB	R/W	rx_enb	Rx Interrupt Enable. If 1 then RXEMPTY=0 or RXOFLO or RXFRAM=1 will interrupt. If 0, masked.
1	URXO	RO	rx_oflo	Rx Data Overflow. Set to 1 when a character has been received but rx_full is still 1.
0	URXM	RO	rx_fram	RXFRAM RX Framing Error. Set to 1 when a stop bit was not detected.

ARC_UART0_BAUD_LO - ARC_UART1_BAUD_LO Registers:	Mode: Normal	Addresses: 0xFFFB0018, 0xFFFB1018	POR: 0x00000000
Register Overview: Baud Rate Low Divisor

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Mne
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Mne									UBDLO

Bit(s)	Mne	Access	Name	Field Description
31:8	RSV	RO	Reserved	Reserved for future use.
7:0	UBDLO	R/W	rate_lo	Baud rate register [7:0]. Baud register values are computed as: Baud register value = (CLK /(BAUD4))-1. Ex: If CLK=12 MHz and you want 19.2k baud, (12e6/(19.2e34))-1=155.

ARC_UART0_BAUD_HI - ARC_UART1_BAUD_HI Registers:	Mode: Normal	Addresses: 0xFFFB001C, 0xFFFB101C	POR: 0x00000000
Register Overview: Baud Rate High Divisor

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Mne
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Mne									UBDHI

Bit(s)	Mne	Access	Name	Field Description
31:8	RSV	RO	Reserved	Reserved for future use.
7:0	UBDHI	R/W	rate_high	Baud rate register [15:8]. Baud register values are computed as: Baud register value = (CLK /(BAUD4))-1. Ex: If CLK=12 MHz and you want 19.2k baud, (12e6/(19.2e34))-1=155.