SOC Block WDOG_TIMER Module Description

Module Overview: This is the timer module for the Bulldog Chip. This timer module consists of: - A Fixed clock divider - A prescaler to create4 a programmable clock divider - 2 Programmable 8-bit timers, timer0 and timer1 - A cascade mode to create a 16-bit timer out of timer0 and timer1, - A Watchdog timer. The fixed clock divider is also used a baud rate generator for serial port control. More about Watchdog Timers

WDOG_TIMER Module Register Summary
Register Name	Base Address	POR
WDOG_TIMER_CTRL	0xFFFC0000	0x00000000
WDOG_TIMER_DATA	0xFFFC0004	0x00000000
WDOG_TIMER01_DATA	0xFFFC0008	0x0000
WDOG_TIMER0_DATA	0xFFFC000A	0x00
WDOG_TIMER1_DATA	0xFFFC000B	0x00
WDOG_TIMER_WATCHDOG	0xFFFC000C	0x00
WDOG_TIMER_PRESCALE_32	0xFFFC0010	0x00000000
WDOG_TIMER_PRESECALE16	0xFFFC0014	0x0000

WDOG_TIMER Module Registers

WDOG_TIMER_CTRL Register:	Mode: Normal	Address: 0xFFFC0000	POR: 0x00000000
Register Overview: Timer Control. A 32-bit write on register to control the operation, clock selection, and divide factor for timer 0 and timer 1.

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Mne	DIV0								DIV1
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Mne	CLK0				CLK1				PRES0		PRES1		INT0	INT1	MODE0	MODE1

Bit(s)	Mne	Access	Name	Field Description
31:24	DIV0	R/W	DIVIDE_0	The divide factor between 1 and 256 for timer 0. See the WDOG_TIMER_0_DATA 8 bit Register
23:16	DIV1	R/W	DIVIDE_1	The divide factor between 1 and 256 for timer 1.
15:12	CLK0	R/W	CLKSEL_0	A set of 15 fixed clock frequency rates. The following enumerations describe the settings. This will be overwritten if the prescale bit is set for the corresponding timer. Enumerations for teTimerClkSel: e0_3kHz = 0 ; Nominal frequency = 0.3kHz e0_6kHz = 1 ; Nominal frequency = 0.6kHz e1_2kHz = 2 ; Nominal frequency = 1.2kHz e2_4kHz = 3 ; Nominal frequency = 2.4kHz e4_8kHz = 4 ; Nominal frequency = 4.8kHz e9_6kHz = 5 ; Nominal frequency = 9.6kHz e19_2kHz = 6 ; Nominal frequency = 19.2kHz e38_4kHz = 7 ; Nominal frequency = 38.4kHz e57_6kHz = 8 ; Nominal frequency = 57.6kHz e115_2kHz = 9 ; Nominal frequency = 115_2kHz e230_4kHz = 10 ; Nominal frequency = 230_4kHz e460_8kHz = 11 ; Nominal frequency = 460_8kHz e921_6kHz = 12 ; Nominal frequency = 921_6kHz e1843_2kHz = 13 ; Nominal frequency = 1843_2kHz e6250_0kHz = 14 ; Nominal frequency = 6250_0kHz eCascade0 = 15 ; Set Timer 1 only to this bit, sets up cascade mode
11:8	CLK1	R/W	CLKSEL_1	A set of 16 fixed clock prescale rates. To put the timers in cascade mode, set this bit to eCascade0. The timer0 interrupt is used to signal athe end count of the cascaded counter. The timer1 interrupt is not used. See the CLKSEL_0 Field
7:6	PRES0	R/W	PRESCALE_0	Controls the prescaler for the timer 0. 0 = Normal 1 = Prescale clock 16 2 = Prescale clock 32 If this bit is set to 1 or 2, it will use the it's corresponding fixed clock select prescale value. It will override the clksel setting.
5:4	PRES1	R/W	PRESCALE_1	Controls the prescaler for the timer 1. 0 = Normal 1 = Prescale clock 16 2 = Prescale clock 32 If this bit is set to 1 or 2, it will use the it's corresponding fixed clock select prescale value. It will override the clksel setting.
3	INT0	R/W1C	INT_0	The Interrupt status of Timer 0. 0 = No Interrupt. 1 = Interrupt has occurred. Setting this bit to 0 has not effect. Setting it to 1 will clear the interrupt.
2	INT1	R/W1C	INT_1	The Interrupt status of Timer 1. 0 = No Interrupt. 1 = Interrupt has occurred. Setting this bit to 0 has not effect. Setting it to 1 will clear the interrupt.
1	MODE0	R/W	MODE_0	The timer 0 mode control. When the timer is started the following is performed: 1. Count down to 1. 2. Generate an interrupt and set the timer's interrupt bit 3. Restarts from the programmed divide factor. If the divide factor is changed while timer is running, it will not take effect until the ongoing count has expired. Valid Modes are 00,01,10, 11 = Reserved Enumerations for teTimermode: eTimerStopAndLoad = 0 ; Stop the timer and load it witht the divide factor. eTimerStopAndPreserve = 1 ; Stop the timer and preserve the current count value. eTimerRun = 2 ; Start the timer as it is programmed.
0	MODE1	R/W	MODE_1	The timer 1 mode control. See Timer Mode 0 Description

WDOG_TIMER_DATA Register:	Mode: Normal	Address: 0xFFFC0004	POR: 0x00000000
Register Overview: A 32-bit read only register for the high and low byte of the fixed clock divider, and the current value of timer0 and timer 1.

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Mne	HCLKD								HCLKD
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Mne	VAL0								VAL1

Bit(s)	Mne	Access	Name	Field Description
31:24	HCLKD	RO	HIGH_CLOCK_DIV	This is the high byte of the clock divider value.
23:16	HCLKD	RO	LOW_CLOCK_DIV	This is the low byte of the clock divider value.
15:8	VAL0	RO	0_CURR_VALUE	This is timer 0's current value.
7:0	VAL1	RO	1_CURR_VALUE	This is timer 1's current value.

WDOG_TIMER01_DATA Register:	Mode: Normal	Address: 0xFFFC0008	POR: 0x0000
Register Overview: This is the value of combined count value of timer 0 and timer 1. Typically used when the timers are cascade coupled.

Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Mne	VAL0								VAL1

Bit(s)	Mne	Access	Name	Field Description
15:8	VAL0	RO	0_VAL	Timer Count Value for timer 0.
7:0	VAL1	RO	1_VAL	Timer Count Value for timer 1.

WDOG_TIMER0_DATA Register:	Mode: Normal	Address: 0xFFFC000A	POR: 0x00
Register Overview: The byte value for the current count of timer 0.

Bit	7	6	5	4	3	2	1	0
Mne	DATA0

Bit(s)	Mne	Access	Name	Field Description
7:0	DATA0	RO	DATA0	Timer 0's current value count.

WDOG_TIMER1_DATA Register:	Mode: Normal	Address: 0xFFFC000B	POR: 0x00
Register Overview: The byte value for the current count of timer 1.

Bit	7	6	5	4	3	2	1	0
Mne	DATA1

Bit(s)	Mne	Access	Name	Field Description
7:0	DATA1	RO	DATA1	Timer 1's current value count.

WDOG_TIMER_WATCHDOG Register:	Mode: Normal	Address: 0xFFFC000C	POR: 0x00
Register Overview: When the watchdog timer is started, it generates an NMI if the watchdog is not stopped or restarted within 0.1 seconds. If iit still is not restarted or stopped after an additional 3.3ms, the watdog timer resets the chip.

Bit	7	6	5	4	3	2	1	0
Mne					KEY			EN

Bit(s)	Mne	Access	Name	Field Description
7:4	RSV	Reserved	Reserved	Reserved
3:1	KEY	R/W	KEY_VALUE	state=stopped; enable=0; key = X; No effect state=stopped; enable=1; key= key_val; Start watchdog with key_val state=started; enable=0; key=~key; Stop watchdog state=started; enable=1; key=~key; Restart watdog with key = ~key state=started; enable=X; new_key_val; Change key to new_key_val
0	EN	R/W	ENABLE	This bit enables the watchdog timer. It used in conjuction with the key described in the previous field.

WDOG_TIMER_PRESCALE_32 Register:	Mode: Normal	Address: 0xFFFC0010	POR: 0x00000000
Register Overview: A 32 bit value for the divide factor for timer and serial clock prescaling.

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Mne
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Mne	PR32

Bit(s)	Mne	Access	Name	Field Description
31:0	PR32	R/W	PRESCALE32	The programmable clock divider divides a 25Mhz clock with a 32-bit value. This prescaler will be used, if the PRESCALE bit for the selected timer is set to 2.

WDOG_TIMER_PRESECALE16 Register:	Mode: Normal	Address: 0xFFFC0014	POR: 0x0000
Register Overview: A 16 bit value for the divide factor for timer clock prescaling.

Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Mne	PR16

Bit(s)	Mne	Access	Name	Field Description
15:0	PR16	R/W	PRESCALE16	The programmable clock divider divides a 25Mhz clock with a 16-bit value. This prescaler will be used, if the PRESCALE bit for the selected timer is set to 1. This 16-bit value ranges from 2 to 64435, and results in new clock availbe for timers that ranges from 12.5Mhz down to 38.5Hz.