| VIDEO Block LCD Module Description |
Module Overview:
This describes all the registers in the LCD Controller.
What is an LCD |
| LCD Module Register Summary | Register Name | Base Address | POR |
| LCD_INT_STATUS | 0xFFF80600 | 0x00000000 |
| LCD_INT_EN | 0xFFF80604 | 0x00000000 |
| LCD_RD_CFG | 0xFFF80608 | 0x00000000 |
| LCD_WRT_CFG | 0xFFF8060C | 0x00000000 |
| LCD_CYCLE_TIME | 0xFFF80610 | 0x00000000 |
| LCD_INT_STATUS Register: | Mode: Normal | Address: 0xFFF80600 | POR: 0x00000000 | |
| Register Overview: This register stores interrupts from the LCD controller to the microprocessor. | ||||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| Mne | ||||||||||||||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Mne | IDLE | FFEMP | ||||||||||||||
| Bit(s) | Mne | Access | Name | Field Description |
| 31:2 | RSV | RO | Reserved | Reserved for future use. |
| 1:1 | IDLE | R/W1C | IDLE | A 1 indicates that the LCD controller's state machine and all other registers are idle after receiving the suspend signal. This field is cleared by writing a 1 to it. |
| 0:0 | FFEMP | R/W1C | FIFO_EMPTY | A 1 indicates that the LCD Write FIFO is empty and that additional data is required. This Field is cleared by writing a 1 to it. |
| LCD_INT_EN Register: | Mode: Normal | Address: 0xFFF80604 | POR: 0x00000000 | |
| Register Overview: This register enables the individual interrupts described in LCD IRQ Status Register. | ||||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| Mne | ||||||||||||||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Mne | IDLE | FFEN | ||||||||||||||
| Bit(s) | Mne | Access | Name | Field Description |
| 31:2 | RSV | RO | Reserved | Reserved for future use. |
| 1:1 | IDLE | R/W | IDLE_EN | Writing a 1 to this bit enables the IDLE interrupt. A 0 disables the IDLE interrupt. |
| 0:0 | FFEN | R/W | FIFO_EMPTY_EN | Writing 1 to this bit enables that the FIFO EMPTY interrupt. A 0 disables the interrupt. |
| LCD_RD_CFG Register: | Mode: Normal | Address: 0xFFF80608 | POR: 0x00000000 | |
| Register Overview: This register controls the timing of the signals to the LCD display during a read operations. | ||||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| Mne | RCSW | RCSET | ||||||||||||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Mne | RDCYL | RDSET | ||||||||||||||
| Bit(s) | Mne | Access | Name | Field Description |
| 31:30 | RSV | RO | Reserved | Reserved for future use. |
| 29:24 | RCSW | R/W | RCS_WIDTH | Number of system clock cycles that chip_select is asserted during a read operation. |
| 23:22 | RSV | RO | Reserved | Reserved for future use. |
| 21:16 | RCSET | R/W | RCS_SETUP | Number of system clock cycles from the assertion of reg_sel signal to the assertion of of the chip_select signal during a read operation. |
| 15:14 | RSV | RO | Reserved | (null) |
| 13:8 | RDCYL | R/W | RD_CYCLE | The number of system clock cycles that the read signal is asserted. |
| 7:6 | RSV | RO | Reserved | Reserved for future use. |
| 5:0 | RDSET | R/W | RD_SETUP | Number of system clock cycles from the assertion of reg_select signal to assertion of the read signal. |
| LCD_WRT_CFG Register: | Mode: Normal | Address: 0xFFF8060C | POR: 0x00000000 | |
| Register Overview: This register controls the timing of the signals to the LCD display during a write operation. | ||||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| Mne | WCSET | WCSET | ||||||||||||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Mne | WRCYC | WSSET | ||||||||||||||
| Bit(s) | Mne | Access | Name | Field Description |
| 31:30 | RSV | RO | Reserved | Reserved for future use. |
| 29:24 | WCSET | R/W | WR_SETUP | Number of system clock cycles from the assertion of the reg_select signal to the assertion of write signal. |
| 23:22 | RSV | RO | Reserved | Reserved for future use. |
| 21:16 | WCSET | R/W | WCS_SETUP | Number of system clock cycles from the assertion of the reg_select signal to assertion of chip_select signal during a write operation. |
| 15:14 | RSV | RO | Reserved | Reserved for future use. |
| 13:8 | WRCYC | R/W | WR_CYCLE | Number of system clock cycles that the write signal is asserted. |
| 7:6 | RSV | RO | Reserved | Reserved for future use. |
| 5:0 | WSSET | R/W | WR_SETUP | The Number of system clock cycles that the chip_select signal is asserted during a write operation. |
| LCD_CYCLE_TIME Register: | Mode: Normal | Address: 0xFFF80610 | POR: 0x00000000 | |
| Register Overview: This register controls the cycle time for both read and write operations. | ||||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| Mne | ||||||||||||||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Mne | CNT | |||||||||||||||
| Bit(s) | Mne | Access | Name | Field Description |
| 31:7 | RSV | RO | Reserved | Reserved for future use. |
| 6:0 | CNT | R/W | COUNT | Number of system clock cycles each read or write to the LCD display takes per operation. |