Barbay Consulting
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Single Point Source TM
The New Way of SoC Development
The New Way of SoC Development
We are a consulting group in Asic Verification, Development, and firmware development.
Our approach is unique. We have people with various backgrounds and think that co-
development is the best. We are a team of Asic designers, Asic VerificationEngineers
(including test plans, test benches, and regression suites), Embedded FW Engineers, and
Technical Marketing Engineers.
We believe in using the lastest tools: Assertions, Coverage, and Random Testing for
White/Black Box Testing, bus checking, and protocol checking. We have now have these
major methodologies that are FREE - VMM, OVM, OVL, IP-XACT 1.5 that support Denali's
SystemRdl. No more technology lock in.
We also believe in having firmware engineers involved in simulation (in the best world -- in a
prototyping environment like FPGAs to speed up debugging). This gives you the best of both
worlds: Architecturally correct SoCs from the firmware perspective (are there enough DMA
channels, audio channels, etc.) and it encourages cooperation between groups (picture a
world having an ASIC and Firmware Engineers debugging together on both plans - virtual
[simulation], reaity[RDK]). You have real firmware running and much of the HAL and some of
the API layers are built by the time Silicon is returned from the Foundry!!!!
We are also experienced in RTOSes, DSPs, Video Technology, Audio Technology, USB and
PCIe technology, as well as Solid State Devices (SCSI, SATA, etc).
Originally we started with this common methodology:
The SPS Tool uses a single point of definition and description of registers written in XML to
be used during the ASIC/SoC development process and produces multiple output files
which will be used in various ways:
Testing written in various language ‘C’, Vera, System ‘C’, Verilog 'C' and customized
assembly language.
The Single Point Source XML input file creates an environment where one single input (XML)
defines the registers in a system. SPS uses this XML dialect file to mechinally create
multiple outputs. This forces a system where outputs dependant on a register change will
be updated and synchronized appropriately. The outputs created are for a range of
customers within the company and reduces “out-of-synch" errors and miscommunication
across the entire product base of developer's of the ASIC within a company and it's
foundary.
The SPS approach has SAVED companies MILLIONS of dollars in SoC miscommunication
and silicon turns at the foundary. SPS REDUCES time to market, and REDUCES cost.
Also the new approach of SVA/PSL and real Firmware being developed at the same time
relieves schedule pressure. No more waiting for the Silicon to come back! Boards can
be brought up in days (maybe even 1 day) - yes we have had that happen for a multi-
million gate chip.
Our approach is unique. We have people with various backgrounds and think that co-
development is the best. We are a team of Asic designers, Asic VerificationEngineers
(including test plans, test benches, and regression suites), Embedded FW Engineers, and
Technical Marketing Engineers.
We believe in using the lastest tools: Assertions, Coverage, and Random Testing for
White/Black Box Testing, bus checking, and protocol checking. We have now have these
major methodologies that are FREE - VMM, OVM, OVL, IP-XACT 1.5 that support Denali's
SystemRdl. No more technology lock in.
We also believe in having firmware engineers involved in simulation (in the best world -- in a
prototyping environment like FPGAs to speed up debugging). This gives you the best of both
worlds: Architecturally correct SoCs from the firmware perspective (are there enough DMA
channels, audio channels, etc.) and it encourages cooperation between groups (picture a
world having an ASIC and Firmware Engineers debugging together on both plans - virtual
[simulation], reaity[RDK]). You have real firmware running and much of the HAL and some of
the API layers are built by the time Silicon is returned from the Foundry!!!!
We are also experienced in RTOSes, DSPs, Video Technology, Audio Technology, USB and
PCIe technology, as well as Solid State Devices (SCSI, SATA, etc).
Originally we started with this common methodology:
The SPS Tool uses a single point of definition and description of registers written in XML to
be used during the ASIC/SoC development process and produces multiple output files
which will be used in various ways:
- Register Transfer Language (RTL) (Verilog or VHDL).
- Embedded firmware for register and bit field definitions in 'C', C++.
- HTML documentation with auto-generated links for Register Tables and bit fields.
- HTML Chip Memory Map.
- HTML Pin I/O Tables using autogenerated SVG for PIN Pad Graphics.
- .CSV for legacy.
- Validation software:
Testing written in various language ‘C’, Vera, System ‘C’, Verilog 'C' and customized
assembly language.
The Single Point Source XML input file creates an environment where one single input (XML)
defines the registers in a system. SPS uses this XML dialect file to mechinally create
multiple outputs. This forces a system where outputs dependant on a register change will
be updated and synchronized appropriately. The outputs created are for a range of
customers within the company and reduces “out-of-synch" errors and miscommunication
across the entire product base of developer's of the ASIC within a company and it's
foundary.
The SPS approach has SAVED companies MILLIONS of dollars in SoC miscommunication
and silicon turns at the foundary. SPS REDUCES time to market, and REDUCES cost.
Also the new approach of SVA/PSL and real Firmware being developed at the same time
relieves schedule pressure. No more waiting for the Silicon to come back! Boards can
be brought up in days (maybe even 1 day) - yes we have had that happen for a multi-
million gate chip.
A Leader in SoC Development Tools
Copyright 2010, Lisa K. Barbay
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